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Freescale Semiconductor Data Sheet: Advance Information
MCF5373DS Rev. 0.3, 04/2006
MCF5373 ColdFire(R) Microprocessor Data Sheet
Supports MCF5372L, MCF5372, MCF5373L, & MCF5373
by: Microcontroller Division
The MCF537x devices are a family of highly-integrated 32-bit microprocessors based on the Version 3 ColdFire microarchitecture. All MCF537x devices contain a 32-Kbyte internal SRAM, a Fast Ethernet controller, a 2-bank SDR/DDR SDRAM controller, a 16-channel DMA controller, up to three UARTs, a queued SPI, as well as other peripherals that enable the MCF537x family for use in general purpose industrial control applications. Optional peripherals include USB host and On-the-Go controllers and cryptography hardware accelerators. This document provides an overview of the MCF537x microprocessor family, focusing on its highly diverse feature set. It was written from the perspective of the MCF5373L device. However, it also pertains to the MCF5372L, MCF5372, and MCF5373. See the following section for a summary of differences between the various devices of the MCF537x family.
Table of Contents
1 2 3 4 5 6 MCF537x Family Configurations .........................2 Ordering Information ...........................................3 Signal Descriptions..............................................3 Mechanicals and Pinouts ....................................8 Preliminary Electrical Characteristics ................14 Revision History ................................................40
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. * Preliminary
MCF537x Family Configurations
1
MCF537x Family Configurations
Table 1. MCF537x Family Configurations
Module ColdFire Version 3 Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock / 3) Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) SDR/DDR SDRAM Controller USB 2.0 Host USB 2.0 On-the-Go Synchronous Serial Interface (SSI) Fast Ethernet Controller (FEC) Cryptography Hardware Accelerators UARTs I2C QSPI PWM Module Real Time Clock 32-bit DMA Timers Watchdog Timer (WDT) Periodic Interrupt Timers (PIT) Edge Port Module (EPORT) Interrupt Controllers (INTC) 16-channel Direct Memory Access (DMA) FlexBus External Interface General Purpose I/O (GPIO) JTAG - IEEE(R) 1149.1 Test Access Port Package x -- -- x x -- 3 x x -- x 4 x 4 x 2 x x up to 46 x 160 QFP x x x x x -- 3 x x x x 4 x 4 x 2 x x up to 62 x 196 MAPBGA MCF5372 MCF5372L MCF5373 MCF5373L x up to 180 MHz up to 60 MHz up to 158 x up to 240 MHz up to 80 MHz up to 211 x up to 180 MHz up to 60 MHz up to 158 x up to 240 MHz up to 80 MHz up to 211
The following table compares the various device derivatives available within the MCF537x family.
16 Kbytes 32 Kbytes x -- -- x x x 3 x x -- x 4 x 4 x 2 x x up to 46 x 160 QFP x x x x x x 3 x x x x 4 x 4 x 2 x x up to 62 x 196 MAPBGA
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 2 Preliminary Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number MCF5372CAB180 MCF5372LCVM240 MCF5373CAB180 MCF5373LCVM240 Description MCF5372 RISC Microprocessor, 160 QFP MCF5372 RISC Microprocessor, 196 MAPBGA MCF5373 RISC Microprocessor, 160 QFP MCF5373 RISC Microprocessor, 256 MAPBGA Speed 180 MHz 240 MHz 180 MHz 240 MHz Temperature -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
3
Signal Descriptions
The following table lists all the MCF537x pins grouped by function. The "Dir" column is the direction for the primary function of the pin only. Refer to Section 4, "Mechanicals and Pinouts," for package diagrams. For a more detailed discussion of the MCF537x signals, consult the MCF5373 Reference Manual (MCF5373RM). NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A23), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality.
Table 3. MCF5372/3 Signal Information and Muxing
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5372 MCF5373 160 QFP MCF5372L MCF5373L 196 MAPBGA
Reset RESET2 RSTOUT -- -- -- -- Clock EXTAL XTAL
2
-- --
I O
95 86
K13 L12
-- -- -- --
-- -- -- --
-- -- -- --
I O I O
91 93 -- --
L14 K14 P13 N13
EXTAL32K XTAL32K
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 3
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name FB_CLK GPIO -- Alternate 1 -- Alternate 2 -- Dir.1 O MCF5372 MCF5373 160 QFP 40 MCF5372L MCF5373L 196 MAPBGA N1
Mode Selection RCON2 DRAMSEL -- -- -- -- FlexBus A[23:22] A[21:16] A[15:14] A[13:11] A10 A[9:0] -- -- -- -- -- -- FB_CS[5:4] -- SD_BA[1:0] SD_A[13:11] -- SD_A[9:0] -- -- -- -- -- -- O O O O O O 134, 133 132-127 126, 123 120-118 11 116-107 A9, B9 C9, D9, A10, B10, C10, D10 A11, B11 C11, A12, B12 A13 A14, B14, B13, C12, D11, C14, C13, D14-D12 J2, J1, K4-K1, L4, L3, N2, P1, P2, N3, L5, P3, N4, P4 F2, F1, G4-G1, H4, H3, L6, M6, N6, P6, L7, M7, N7 P7 J3, M5, H2, P5 M8 E14 L8 E2 -- -- I I 72 92 P8 J11
D[31:16]
--
SD_D[31:16]3
--
O
27-34, 46-53
D[15:1]
--
FB_D[31:17]3
--
O
16-23, 57-63
D02 BE/BWE[3:0] OE TA2 R/W TS
-- PBE[3:0] PBUSCTL3 PBUSCTL2 PBUSCTL1 PBUSCTL0
FB_D[16]3 SD_DQM[3:0] -- -- -- DACK0 Chip Selects
-- -- -- -- -- --
O O O I O O
64 26, 54, 24, 56 66 106 65 12
FB_CS[5:4] FB_CS[3:2] FB_CS1 FB_CS0
PCS[5:4] PCS[3:2] PCS1 --
-- -- -- --
-- -- -- --
O O O O
-- -- 135 136
D8, C8 B8, A8 D7 C7
SDRAM Controller SD_A10 SD_CKE -- -- -- -- -- -- O O 43 14 M2 F4
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 4 Preliminary Freescale Semiconductor
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name SD_CLK SD_CLK SD_CS0 SD_DQS3 SD_DQS2 SD_SCAS SD_SRAS SD_SDR_DQS SD_WE GPIO -- -- -- -- -- -- -- -- -- Alternate 1 -- -- -- -- -- -- -- -- -- Alternate 2 -- -- -- -- -- -- -- -- -- Dir.1 O O O O O O O O O MCF5372 MCF5373 160 QFP 37 38 15 25 55 44 45 35 13 MCF5372L MCF5373L 196 MAPBGA L1 M1 F3 H1 N5 M3 M4 L2 E1
External Interrupts Port4 IRQ72 IRQ62 IRQ52 IRQ42 IRQ32 IRQ22 IRQ12 PIRQ72 PIRQ62 PIRQ52 PIRQ42 PIRQ32 PIRQ22 PIRQ12 -- USBHOST_ VBUS_EN2 USBHOST_ VBUS_OC2 SSI_MCLK2 -- USB_CLKIN2 DREQ12 FEC FEC_MDC FEC_MDIO FEC_COL FEC_CRS FEC_RXCLK FEC_RXDV FEC_RXD[3:0] FEC_RXER FEC_TXCLK FEC_TXEN FEC_TXER FEC_TXD[3:0] PFECI2C3 PFECI2C2 PFECH7 PFECH6 PFECH5 PFECH4 PFECH[3:0] PFECL7 PFECL6 PFECL5 PFECL4 PFECL[3:0] I2C_SCL2 I2C_SDA2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O I/O I I I I I I I O O O 4 3 144 145 146 147 148-151 152 153 154 155 157, 158, 1, 2 B1 A1 B6 A6 A5 B5 C5, D5, A4, B4 C4 A3 B3 A2 D4, C3, B2, C2 -- -- -- -- -- -- SSI_CLKIN I I I I I I I 102 -- -- 101 -- -- 100 F13 F12 F11 G14 G13 G12 G11
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 5
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5372 MCF5373 160 QFP MCF5372L MCF5373L 196 MAPBGA
USB Host & USB On-the-Go USBOTG_M USBOTG_P USBHOST_M USBHOST_P -- -- -- -- -- -- -- -- PWM PWM7 PWM5 PWM3 PWM1 PPWM7 PPWM5 PPWM3 PPWM1 -- -- DT3OUT DT2OUT SSI The SSI signals do not have dedicated bond pads. Please refer to the following pins for muxing: IRQ4 for SSI_MCLK, IRQ1 for SSI_CLKIN, U1CTS for SSI_BCLK, U1RTS for SSI_FS, U1RXD for SSI_RXD, and U1TXD for SSI_TXD I2C I2C_SCL2 I2C_SDA2 PFECI2C1 PFECI2C0 -- -- DMA DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing: TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1. QSPI QSPI_CS2 QSPI_CS1 QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT PQSPI5 PQSPI4 PQSPI3 PQSPI2 PQSPI1 PQSPI0 U2RTS PWM7 PWM5 I2C_SCL2 U2CTS I2C_SDA2 UARTs U1CTS U1RTS U1TXD U1RXD U0CTS PUARTL7 PUARTL6 PUARTL5 PUARTL4 PUARTL3 SSI_BCLK SSI_FS SSI_TXD2 SSI_RXD2 -- -- -- -- -- -- I O O I I 143 142 141 140 85 C6 D6 A7 B7 M14 -- USBOTG_ PU_EN -- -- -- -- O O O O I O 78 -- -- 77 75 76 N12 M12 M11 P12 P11 N11 U2TXD U2RXD I/O I/O -- -- E3 E4 -- -- DT3IN DT2IN I/O I/O I/O I/O -- -- -- -- E13 E12 E11 F14 -- -- -- -- I/O I/O I/O I/O -- -- -- -- H14 H13 J13 J12
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 6 Preliminary Freescale Semiconductor
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name U0RTS U0TXD U0RXD GPIO PUARTL2 PUARTL1 PUARTL0 Alternate 1 -- -- -- Alternate 2 -- -- -- Dir.1 O O I MCF5372 MCF5373 160 QFP 84 83 80 MCF5372L MCF5373L 196 MAPBGA M13 N14 P14
Note: The UART2 signals are multiplexed on the QSPI, DMA Timers, and I2C pins. DMA Timers DT3IN DT2IN DT1IN DT0IN PTIMER3 PTIMER2 PTIMER1 PTIMER0 DT3OUT DT2OUT DT1OUT DT0OUT U2RXD U2TXD DACK1 DREQ02 I I I I 8 7 6 5 D1 C1 D2 D3
BDM/JTAG5 JTAG_EN6 DSCLK PSTCLK BKPT DSI DSO DDATA[3:0] PST[3:0] ALLPST -- -- -- -- -- -- -- -- -- -- TRST2 TCLK2 TMS2 TDI2 TDO -- -- -- Test TEST6 -- -- -- I 124 E10 -- -- -- -- -- -- -- -- -- I I O I I O O O O 96 88 70 87 90 74 -- -- 73 G10 K11 N8 L13 K12 L11 L9, M9, N9, P9 L10, M10, N10, P10 --
Power Supplies EVDD -- -- -- 9, 69, 71, 81, 94, 103, 139, 160 36, 79, 97, 125, 156 99 11, 39, 41, 67, 105, 121, 137 E6, E7, F5-F7, G5, H10, J8, K8-K9 E5, J9, K5, K10 J10 E8-E9, F8-F10, J4-J7, H5, K6, K7
IVDD PLL_VDD SD_VDD
-- -- --
-- -- --
-- -- --
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 7
Mechanicals and Pinouts
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name USBOTG_VDD VSS GPIO -- -- Alternate 1 -- -- Alternate 2 -- -- Dir.1 MCF5372 MCF5373 160 QFP -- 10, 42, 68, 82, 89, 104, 122, 138, 159 98 -- MCF5372L MCF5373L 196 MAPBGA H12 G6-G9, H6-H9
PLL_VSS USBHOST_VSS
-- --
-- --
-- --
H11 J14
NOTES: 1 Refers to pin's primary function. 2 Pull-up enabled internally on this signal for this mode. 3 Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins. 4 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. 5 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 6 Pull-down enabled internally on this signal for this mode.
4
Mechanicals and Pinouts
NOTE The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire.
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF537x devices.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 8 Preliminary Freescale Semiconductor
Mechanicals and Pinouts
4.1
1 A FEC_ MDIO FEC_ MDC
Pinout--196 MAPBGA
2 FEC_ TXER FEC_ TXD1 FEC_ TXD0 3 FEC_ TXCLK FEC_ TXEN FEC_ TXD2 4 FEC_ RXD1 FEC_ RXD0 FEC_ RXER FEC_ TXD3 5 FEC_ RXCLK FEC_ RXDV FEC_ RXD3 FEC_ RXD2 6 FEC_ CRS FEC_ COL 7 U1TXD 8 FB_CS2 9 A23 10 A19 11 A15 12 A12 13 A10 14 A9 A
The pinout for the MCF5373LCVM240 and MCF5372LCVM240 packages are shown below.
B
U1RXD
FB_CS3
A22/
A18
A14
A11
A7
A8
B
C
DT2IN
U1CTS
FB_CS0 FB_CS4
A21
A17
A13
A6
A3
A4
C
D
DT3IN
DT1IN
DT0IN
U1RTS
FB_CS1 FB_CS5
A20
A16
A5
A0
A1
A2
D
E
SD_WE
TS
I2C_SCL I2C_SDA
IVDD
EVDD
EVDD
SD_VDD SD_VDD
TEST
PWM3
PWM5
PWM7
TA
E
F
D14
D15
SD_CS0
SD_CKE
EVDD
EVDD
EVDD
SD_VDD SD_VDD SD_VDD
IRQ5
IRQ6
IRQ7
PWM1
F
G
D10
D11
D12
D13
EVDD
VSS
VSS
VSS
VSS
JTAG_ EN
IRQ1
IRQ2
IRQ3
IRQ4
G
H
SD_ DQS3
BE/ BWE1
D8
D9
SD_VDD
VSS
VSS
VSS
VSS
EVDD
PLL_ VSS DRAM SEL TRST/ DSCLK TDO/ DSO QSPI_ CS0 QSPI_ DOUT QSPI_ DIN 11
USBOTG _VDD
USB OTG_P
USB OTG_M
H
J
D30
D31
BE/ BWE3
SD_VDD SD_VDD SD_VDD SD_VDD
EVDD
IVDD
PLL_ VDD
USB USB USBHOST J HOST_P HOST_M _VSS
K
D26
D27
D28
D29
IVDD
SD_VDD SD_VDD
EVDD
EVDD
IVDD
TDI/DSI
RESET
XTAL
K
L
SD_CLK
SD_DR_ DQS
D24
D25
D19
D7
D3
R/W
DDATA3
PST3
RSTOUT
TMS/ BKPT
EXTAL
L
M SD_CLK SD_A10
SD_CAS
SD_RAS
BE/ BWE2 SD_ DQS2 BE/ BWE0 5
D6
D2
OE
DDATA2
PST2
QSPI_ CS1 QSPI_ CS2 QSPI_ CLK 12
U0RTS
U0CTS
M
N
FB_CLK
D23
D20
D17
D5
D1
TCLK/ DDATA1 PSTCLK
PST1
XTAL 32K EXTAL 32K 13
U0TXD
N
P
D22 1
D21 2
D18 3
D16 4
D4 6
D0 7
RCON 8
DDATA0 9
PST0 10
U0RXD 14
P
Figure 1. MCF5373LCVM240 Pinout Top View (196 MAPBGA)
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 9
Mechanicals and Pinouts
4.2
X Y
Package Dimensions--196 MAPBGA
D Laser mark for pin 1 identification in this area NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
Millimeters DIM Min Max
Figure 2 shows the MCF5373LCVM240 and MCF5372LCVM240 package dimensions.
M K
E
A A1 A2 b D E e S
1.32 1.75 0.27 0.47 1.18 REF 0.35 0.65 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
Top View
0.20
13X
M
e Metalized mark for pin 1 identification in this area
A B C
S
14 13 12 11 10 9 6 5 4 3 2 1
S
13X
D E F G H J K L M N
5 A A2 0.30 Z
e
A1
Z
4
0.15 Z
Detail K Rotated 90 Clockwise
3
196X
P
b 0.30 Z X Y 0.10 Z
Bottom View
View M-M
Figure 2. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 10 Preliminary Freescale Semiconductor
Mechanicals and Pinouts
4.3
Pinout--160 QFP
FEC_RXD2 FEC_RXD3 FEC_RXDV FEC_RXCLK FEC_CRS FEC_COL U1CTS U1RTS U1TXD U1RXD 160 EVDD 159 VSS 158 FEC_TXD2 157 FEC_TXD3 156 IVDD 155 FEC_TXER 154 FEC_TXEN 153 FEC_TXCLK 152 FEC_RXER 151 FEC_RXD0 150 FEC_RXD1 EVDD VSS SD_VDD FB_CS0 FB_CS1 A23/FB_CS5 A22/FB_CS4 A21 A20 A19 A18 A17 A16 A15 IVDD TEST A14 VSS SD_VDD 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
The pinout for the MCF5372CAB180 and MCF5373CAB180 packages is shown below.
FEC_TXD1 FEC_TXD0 FEC_MDIO FEC_MDC DT0IN DT1IN DT2IN DT3IN EVDD VSS SD_VDD TS SD_WE SD_CKE SD_CS0 D15 D14 D13 D12 D11 D10 D9 D8 BE/BWE1 SD_DQS1/3 BE/BWE3 D31 D30 D29 D28 D27 D26 D25 D24 SD_DR_DQS IVDD SD_CLK SD_CLK SD_VDD FB_CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
*
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TA SD_VDD VSS EVDD IRQ7 IRQ4 IRQ1 PLL_VDD PLL_VSS IVDD JTAG_EN RESET EVDD XTAL DRAMSEL EXTAL TDI/DSI VSS TRST/DSCLK TMS/BKPT RSTOUT U0CTS U0RTS U0TXD VSS EVDD
Figure 3. MCF5372CAB180 and MCF5373CAB180 Pinout Top View (160 QFP)
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 11
D2 D1 D0 R/W OE SD_VDD VSS EVDD TCLK/PSTCLK EVDD RCON ALL_PST TDO/DSO QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS2 IVDD U0RXD
SD_VDD VSS SD_A10 SD_CAS SD_RAS D23 D22 D21 D20 D19 D18
D17 D16 BE/BWE2 SD_DQS0/2 BE/BWE0 D7 D6 D5 D4 D3
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Mechanicals and Pinouts
4.4
Package Dimensions--160 QFP
Figure 4 and Figure 5 show the MCF5372CAB180 and MCF5373CAB180 package dimensions.
Top View
Figure 4. 160QFP Package Dimensions (Sheet 1 of 2)
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 12 Preliminary Freescale Semiconductor
Mechanicals and Pinouts
Figure 5. 160QFP Package Dimensions (Sheet 2 of 2)
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 13
Preliminary Electrical Characteristics
5
Preliminary Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5373 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5373. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this MCU document supersede any values found in the module specifications.
5.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage CMOS Pad Supply Voltage DDR/Memory Pad Supply Voltage PLL Supply Voltage Digital Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range Symbol IVDD EVDD SDVDD PLLVDD VIN ID TA (TL - TH) Tstg Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to +2.0 - 0.3 to +3.6 25 - 40 to +85 - 55 to +150 Unit V V V V V mA C C
NOTES: 1 Functional operating conditions are given in Section 5.4, "DC Electrical Specifications." Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or EVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to VSS and EVDD.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 14 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
5
Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Insure external EVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions.
5.2
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic Symbol Four layer board (2s2p) Four layer board (2s2p) JMA JMA JB JC jt Tj 256MBGA 261,2 231,2 153 104 21,5 105 196MBGA 321,2 291,2 203 104 21,5 105 160QFP 401,2 361,2 253 104 21,5 105 Unit C/W C/W C/W C/W C/W
oC
Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
NOTES: 1 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA )
Eqn. 1
Where:
TA QJMA PD PINT PI/O = Ambient Temperature, C = Package Thermal Resistance, Junction-to-Ambient, C/W = PINT + PI/O = IDD x IVDD, Watts - Chip Internal Power = Power Dissipation on Input and Output Pins -- User Determined
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 15
Preliminary Electrical Characteristics
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K P D = -------------------------------( T J + 273C )
Eqn. 2
Solving equations 1 and 2 for K gives:
K = P D x ( T A x 273C ) + Q JMA x P D
2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
5.3
ESD Protection
Table 6. ESD Protection Characteristics1, 2
Characteristics ESD Target for Human Body Model Symbol HBM Value 2000 Units V
NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic Symbol IVDD PLLVDD EVDD SDVDD SDVDD SDVDD USBVDD EVIH EVIL SDVIH SDVIL SDVIH SDVIL Min 1.4 1.4 3.0 1.65 2.25 3.0 3.0 2 -0.05 TBD -0.05 2 -0.05 Max 1.6 1.6 3.6 1.95 2.75 3.6 3.6 EVDD + 0.05 0.8 SDVDD + 0.05 TBD SDVDD + 0.05 0.8 Unit V V V V V V V V V V V V V
Core Supply Voltage PLL Supply Voltage CMOS Pad Supply Voltage Mobile DDR/Bus Pad Supply Voltage DDR/Bus Pad Supply Voltage SDR/Bus Pad Supply Voltage USB Supply Voltage CMOS Input High Voltage CMOS Input Low Voltage Mobile DDR/Bus Input High Voltage Mobile DDR/Bus Input Low Voltage DDR/Bus Input High Voltage DDR/Bus Input Low Voltage
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 16 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic Input Leakage Current Vin = VDD or VSS, Input-only pins CMOS Output High Voltage IOH = -5.0 mA CMOS Output Low Voltage IOL = 5.0 mA DDR/Bus Output High Voltage IOH = -5.0 mA DDR/Bus Output Low Voltage IOL = 5.0 mA Weak Internal Pull-Up Device Current, tested at VIL Max.1 Input Capacitance All input-only pins All input/output (three-state) pins
2
Symbol Iin EVOH EVOL SDVOH SDVOL IAPU Cin
Min -1.0 EVDD - 0.4 -- SDVDD - 0.4 -- -10 -- --
Max 1.0 -- 0.4 -- 0.4 -130 7 7
Unit A V V V V A pF
NOTES: 1 Refer to the signals section for pins having weak internal pull-up devices. 2 This parameter is characterized before qualification rather than 100% tested.
5.4.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 6 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible.
10 Board VDD 10 F 0.1 F PLL VDD Pin
GND
Figure 6. System PLL VDD Power Filter
5.4.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 7 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 17
Preliminary Electrical Characteristics 0 Board EVDD/IVDD 10 F 0.1 F USB VDD Pin
GND
Figure 7. USB VDD Power Filter
NOTE In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown.
5.4.3
Supply Voltage Sequencing and Separation Cautions
Figure 8 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PLLVDD), and Core VDD (IVDD).
EVDD, SDVDD, USBVDD Supplies Stable 2.5V SDVDD (2.5V/1.8V)
DC Power Supply Voltage
3.3V
1.5V
1
IVDD, PLLVDD
2
0 Time Notes: 1. IVDD should not exceed EVDD, SDVDD or PLLVDD by more than 0.4 V at any time, including power-up. 2. Recommended that IVDD/PLLVDD should track EVDD/SDVDD up to 0.9 V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PLLVDD) by more than 0.5 V at any time, including during power-up. 4. Use 1 ms or slower rise time for all supplies.
Figure 8. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 18 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
5.4.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 s to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 s or slower rise time for all supplies. 2. IVDD/PLLVDD and EVDD/SDVDD should track up to 0.9 V, then separate for the completion of ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
5.4.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop IVDD/PLLVDD to 0 V. 2. Drop EVDD/SDVDD supplies.
5.5
Power Consumption Specifications
Estimated maximum RUN mode power consumption measurements are shown in the below figure.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 19
Preliminary Electrical Characteristics
Estimated Power Consumption vs. Core Frequency 300 250 200 150 100 50 0 0 40 80 120 160 200 240 Core Frequency (MHz)
Figure 9. Estimated Maximum RUN Mode Power Consumption
Table 8 lists estimated maximum power and current consumption for the device in various operating modes.
Table 8. Estimated Maximum Power Consumption Specifications
Characteristic Run Mode - Total Power Dissipation Static Dynamic Core Operating Supply Current 1 Run Mode Pad Operating Supply Current Run Mode (application dependent) Wait Mode Stop Mode IDD -- EIDD -- -- -- 144 96 1 mA mA mA TBD mA Symbol Typical -- -- -- Max 250 5.74 244 Unit mW mW mW
Power Consumption (mW)
NOTES: 1 Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 20 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
5.6
Num 1
Oscillator and PLL Electrical Characteristics
Table 9. PLL Electrical Characteristics
Characteristic PLL Reference Frequency Range Crystal reference External reference Core frequency CLKOUT Frequency1 Crystal Start-up Time2, 3 EXTAL Input High Voltage Crystal Mode4 All other modes (External, Limp) EXTAL Input Low Voltage Crystal Mode4 All other modes (External, Limp) XTAL Load Capacitance2 PLL Lock Time Duty Cycle of
2, 5
Symbol
Min. Value TBD TBD TBD TBD -- TBD TBD TBD TBD 5
Max. Value 16 16 240 80 10 TBD TBD TBD TBD 30 1 60
Unit
fref_crystal fref_ext fsys fsys/3 tcst VIHEXT VIHEXT VILEXT VILEXT
MHz MHz MHz MHz ms V V V V pF ms %
2 3 4
5
6 7 8
tlpll tdc
-- 40
reference 2
NOTES: 1 All internal registers retain data at 0 Hz. 2 This parameter is guaranteed by characterization before qualification rather than 100% tested. 3 Proper PC board layout procedures must be followed to achieve specifications. 4 This parameter is guaranteed by design rather than 100% tested. 5 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).
5.7
External Interface Timing Characteristics
NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. All other timing relationships can be derived from these values. Timings listed in Table 10 are shown in Figure 11 and Figure 12.
Table 10 lists processor bus input timings.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 21
Preliminary Electrical Characteristics * The timings are also valid for inputs sampled on the negative clock edge. FB_CLK (80MHz)
TSETUP THOLD 1.5V
Input Setup And Hold
Invalid
1.5V
Valid
1.5V
Invalid
trise
Input Rise Time
Vh = VIH Vl = VIL
tfall
Input Fall Time
Vh = VIH Vl = VIL
FB_CLK
B4 B5
Inputs
Figure 10. General Input Timing Requirements
5.7.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
5.7.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 22 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 10. FlexBus AC Timing Specifications
Num Frequency of Operation FB1 FB2 FB3 FB4 FB5 FB6 FB7 FB8 FB9 Clock Period (FB_CLK) Address, Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) Address, Data, and Control Output Hold (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) Data Input Setup Data Input Hold Transfer Acknowledge (TA) Input Setup Transfer Acknowledge (TA) Input Hold Address Output Valid (A[23:0]) Address Output Hold (A[23:0]) tFBCK tFBCHDCV tFBCHDCI tDVFBCH tDIFBCH tCVFBCH tCIFBCH tFBCHAV tFBCHAI Characteristic Symbol Min -- -- -- 1 3.5 0 4 0 -- 1 Max 80 12.5 7.0 -- -- -- -- -- 6.0 -- Unit Mhz ns ns ns ns ns ns ns ns ns
3
Notes fsys/3 tcyc
1
1, 2
NOTES: 1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8.2, "DDR SDRAM AC Timing Characteristics" for SD_CS[3:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the MCF5373 Reference Manual for more information. 3 These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.
FB_CLK
FB1 FB3
A[23:0]
FB2
A[23:0]
FB5
D[31:0]
DATA
R/W
FB4
TS FB_CSn BE/BWEn
FB7
OE
FB6
TA
Figure 11. FlexBus Read Timing.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 23
Preliminary Electrical Characteristics
FB_CLK
FB1 FB3
A[23:0]
FB2 FB3
D[31:0]
R/W
TS FB_CSn BE/BWEn
FB7
OE
FB6
TA
Figure 12. Flexbus Write Timing
5.8
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.8.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device's SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage.
Table 11. SDR Timing Specifications
Symbol Characteristic Frequency of Operation SD1 SD2 SD3 Clock Period Clock Skew Pulse Width High tSDCK tSDSK tSDCKH Symbol Min TBD 12.5 -- 0.45 Max 80 TBD TBD 0.55 SD_CLK
3
Unit Mhz ns
Notes
1 2
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 24 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. SDR Timing Specifications (continued)
Symbol SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 Pulse Width Low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold SD_SDR_DQS Output Valid SD_DQS[3:0] input setup relative to SD_CLK SD_DQS[3:2] input hold relative to SD_CLK Data (D[31:0]) Input Setup relative to SD_CLK (reference only) Data Input Hold relative to SD_CLK (reference only) Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold Characteristic Symbol tSDCKH tSDCHACV tSDCHACI tDQSOV tDQVSDCH tDQISDCH tDVSDCH tDISDCH tSDCHDMV tSDCHDMI Min 0.45 -- 2.0 -- 0.25 x SD_CLK Max 0.55 0.5 x SD_CLK + 1.0 -- Self timed 0.40 x SD_CLK Unit SD_CLK ns ns ns ns
5 6
Notes
4
Does not apply. 0.5xSD_CLK fixed width. 0.25 x SD_CLK 1.0 -- 1.5 -- -- 0.75 x SD_CLK + 0.5 -- ns ns ns ns
7
8
NOTES: 1 The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock. Please see the PLL chapter of the MCF5373 Reference Manual for more information on setting the SDRAM clock rate. 2 SD_CLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 Pulse width high plus pulse width low cannot exceed min and max clock period. 5 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat. 6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat. 7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. 8 Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is just provided as guidance.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 25
Preliminary Electrical Characteristics
SD2 SD_CLK0 SD2 SD_CLK1
SD1
SD3
SD4
SD6 SD_CSn SD_RAS SD_CAS SD_WE A[23:0] SD_BA[1:0]
CMD
SD5
ROW
COL
SD12
SDDM SD13 D[31:0]
WD1
WD2
WD3
WD4
Figure 13. SDR Write Timing
SD2 SD_CLK0 SD2 SD_CLK1 SD_CSn, SD_RAS, SD_CAS, SD_WE A[23:0], SD_BA[1:0] SD6 SD1
CMD
SD5
3/4 MCLK Reference
ROW
COL
tDQS
SDDM SD7 SD_DQS
(Measured at Output Pin) Board Delay
SD9
SD_DDQS
(Measured at Input Pin) Board Delay
SD8
Delayed SD_CLK SD10 D[31:0] from Memories
WD1 WD2 WD3 WD4
NOTE: Data driven from memories relative to delayed memory clock.
SD11
Figure 14. SDR Read Timing
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 26 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
5.8.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early board design. Please contact your local Freescale representative if questions develop.
Table 12. DDR Timing Specifications
Num Characteristic Frequency of Operation DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 Clock Period Pulse Width High Pulse Width Low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode) Input Data Skew Relative to DQS (Input Setup) Symbol tDDCK tDDSK tDDCKH tDDCKL tSDCHACV tSDCHACI tCMDVDQ tDQDMV tDQDMI tDVDQ tDIDQ Min 80 TBD 0.45 0.45 -- 2.0 -- 1.5 1.0 -- 0.25 x SD_CLK + 0.5ns 0.5 0.9 0.4 0.25 0.4 0.6 Max TBD 12.5 0.55 0.55 0.5 x SD_CLK + 1.0 -- 1.25 -- -- 1 -- -- 1.1 0.6 Unit Mhz ns SD_CLK SD_CLK ns ns SD_CLK ns ns ns ns ns SD_CLK SD_CLK SD_CLK SD_CLK
5 6 7
Notes
1 2 3 3 4
8 9
DD10 Input Data Hold Relative to DQS.
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH DD12 DQS input read preamble width DD13 DQS input read postamble width DD14 DQS output write preamble width DD15 DQS output write postamble width tDQRPRE tDQRPST tDQWPRE tDQWPST
NOTES: 1 The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same frequency as the internal bus clock. 2 SD_CLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. 5 This specification relates to the required input setup time of today's DDR memories. Rigoletto's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 6 The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats will be valid for each subsequent DQS edge. 7 This specification relates to the required hold time of today's DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 27
Preliminary Electrical Characteristics
8
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 9 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid.
SD_CLK VIX VMP VIX SD_CLK VID
Figure 15. SD_CLK and SD_CLK crossover timing
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
CMD
DD6
ROW
COL
DD7
DM3/DM2 DD8 SD_DQS3/SD_DQS2 DD7 D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DD8
Figure 16. DDR Write Timing
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 28 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
CL=2
CMD CL=2.5 ROW COL DQS Read Preamble
DD10 DD9
SD_DQS3/SD_DQS2 CL = 2
DQS Read Postamble
D[31:24]/D[23:16]
SD_DQS3/SD_DQS2 CL = 2.5
WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 17. DDR Read Timing
5.9
Num G1 G2 G3 G4
General Purpose I/O Timing
Table 13. GPIO Timing1
Characteristic FB_CLK High to GPIO Output Valid FB_CLK High to GPIO Output Invalid GPIO Input Valid to FB_CLK High FB_CLK High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
NOTES: 1 GPIO pins include: IRQn, PWM, UART, and Timer pins.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 29
Preliminary Electrical Characteristics
FB_CLK
G1
GPIO Outputs
G2
G3
GPIO Inputs
G4
Figure 18. GPIO Timing
5.10 Reset and Configuration Override Timing
Table 14. Reset and Configuration Override Timing
Num R1 R2 R3 R4 R5 R6 R7 R8 Characteristic RESET Input valid to FB_CLK High FB_CLK High to RESET Input invalid RESET Input valid Time 1 FB_CLK High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ Min 9 1.5 5 -- 0 20 0 -- Max -- -- -- 10 -- -- -- 1 Unit ns ns tCYC ns ns tCYC ns tCYC
NOTES: 1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1 R3
RESET
R2
R4
RSTOUT
R4 R8 R5 R6 R7
Configuration Overrides*: (RCON, Override pins])
Figure 19. RESET and Configuration Override Timing
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 30 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
NOTE Refer to the CCM chapter of the MCF5373 Reference Manual for more information.
5.11 USB On-The-Go
The MCF5373 device is compliant with industry standard USB 2.0 specification.
5.12 SSI Timing Specifications
The following figure and table lists the specifications for the SSI module.
S1 S2 S3
SSI_BCLK
S4 S5
SSI_MCLK
STFS
S6
S7
SSI_TXD (Output)
STFS
S6
SSI_RXD (Input) Note: SSI External. Continous clock Synchronous mode only
Figure 20. SSI External Continous Clock Timing Diagram Table 15. SSI Timing
1.8 +/- 0.10V Num S1 S2 S3 SSI_BCLK clock period SSI_BCK high-level time SSI_BCK low-level time Description Minimum 1/(64fs)1 35 35 Maximum 49 -- -- ns ns ns Unit
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 31
Preliminary Electrical Characteristics
Table 15. SSI Timing (continued)
1.8 +/- 0.10V Num S4 S5 S6 S7 Description Minimum SSI_BCK rising edge to SSI_MCLK edge SSI_MCLK edge to SSI_BCLK rising edge SSI_TXD/SSI_RXD data set-up time SSI_TXD/SSI_RXD data hold time 10 10 10 10 Maximum -- -- -- -- ns ns ns ns Unit
NOTES: 1 fs is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz
5.13 I2C Input/Output Timing Specifications
Table 16 lists specifications for the I2C input timing parameters shown in Figure 21.
Table 16. I2C Input Timing Specifications between SCL and SDA
Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 -- 0 -- 4 0 2 2 Max -- -- 1 -- 1 -- -- -- -- Units tcyc tcyc ms ns ms tcyc ns tcyc tcyc
Table 17 lists specifications for the I2C output timing parameters shown in Figure 21.
Table 17. I2C Output Timing Specifications between SCL and SDA
Num I11 I2 I3
1 2
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 10 -- 7 -- 10 2 20 10
Max -- -- -- -- 3 -- -- -- --
Units tcyc tcyc s tcyc ns tcyc tcyc tcyc tcyc
I4 1 I5 3 I6 I7
1 1
I8 1 I9 1
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 32 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics NOTES: 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 17 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 21 shows timing for the values in Table 17 and Table 16.
I5 I2 I2C_SCL I1 I2C_SDA I4 I7 I8 I9 I6
I3
Figure 21. I2C Input/Output Timings
5.14 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
5.14.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV, FEC_RXER, and FEC_RXCLK)
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_RXCLK frequency. Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold FEC_RXCLK pulse width high FEC_RXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns FEC_RXCLK period FEC_RXCLK period
Figure 22 shows MII receive signal timings listed in Table 18.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 33
Preliminary Electrical Characteristics
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs) FEC_RXDV FEC_RXER
M1 M2
Figure 22. MII Receive Signal Timing Diagram
5.14.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK)
Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TXCLK frequency. The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it.
Table 19. MII Transmit Signal Timing
Num M5 M6 M7 M8 Characteristic FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid FEC_TXCLK pulse width high FEC_TXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns FEC_TXCLK period FEC_TXCLK period
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 34 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 23 shows MII transmit signal timings listed in Table 19.
M7
FEC_TXCLK (input)
M5
FEC_TXD[3:0] (outputs) FEC_TXEN FEC_TXER
M6
M8
Figure 23. MII Transmit Signal Timing Diagram
5.14.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 20 lists MII asynchronous inputs signal timing.
Table 20. MII Async Inputs Signal Timing
Num M9 Characteristic FEC_CRS, FEC_COL minimum pulse width Min 1.5 Max -- Unit FEC_TXCLK period
Figure 24 shows MII asynchronous input timings listed in Table 20.
FEC_CRS FEC_COL M9
Figure 24. MII Async Inputs Timing Diagram
5.14.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 21. MII Serial Management Channel Timing
Num M10 M11 M12 M13 Characteristic FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) FEC_MDIO (input) to FEC_MDC rising edge setup FEC_MDIO (input) to FEC_MDC rising edge hold Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 35
Preliminary Electrical Characteristics
Table 21. MII Serial Management Channel Timing (continued)
Num M14 M15 Characteristic FEC_MDC pulse width high FEC_MDC pulse width low Min Max Unit
40% 60% FEC_MDC period 40% 60% FEC_MDC period
Figure 25 shows MII serial management channel timings listed in Table 21.
M14 M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 25. MII Serial Management Channel Timing Diagram
5.15 32-Bit Timer Module Timing Specifications
Table 22 lists timer module AC timings.
Table 22. Timer Module AC Timing Specifications
Name T1 T2 Characteristic Min DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width 3 1 Max -- -- tCYC tCYC Unit
5.16 QSPI Electrical Specifications
Table 23 lists QSPI timings.
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 36 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 23. QSPI Modules AC Timing Specifications
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[3:0] to QSPI_CLK QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) Characteristic Min 1 -- 2 9 9 Max 510 10 -- -- -- Unit tCYC ns ns ns ns
The values in Table 23 correspond to Figure 26.
QS1
QSPI_CS[3:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 26. QSPI Timing
5.17 JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT Min DC 4 26 0 4 26 0 0 4 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- Unit fsys/3 tCYC ns ns ns ns ns ns ns ns
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 37
Preliminary Electrical Characteristics
Table 24. JTAG and Boundary Scan Timing (continued)
Num J11 J12 J13 J14
1
Characteristics1 TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High
Symbol tTDODV tTDODZ tTRSTAT tTRSTST
Min 0 0 100 10
Max 26 8 -- --
Unit ns ns ns ns
NOTES: JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2 J3 VIH J3
TCLK (input)
J4
VIL J4
Figure 27. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 28. Boundary Scan (JTAG) Timing
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 38 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 29. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 30. TRST Timing
5.18 Debug AC Timing Specifications
Table 25 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 25. Debug AC Timing Specification
Num DE0 DE1 DE2 DE3 DE4 DE51 DE6 DE7 PSTCLK cycle time PST valid to PSTCLK high PSTCLK high to PST invalid DSCLK cycle time DSI valid to DSCLK high DSCLK high to DSO invalid BKPT input data setup time to FB_CLK high FB_CLK high to BKPT invalid Characteristic Min -- 4 1.5 5 1 4 4 0 Max 0.3 -- -- -- -- -- -- -- tcyc ns ns tcyc tcyc tcyc ns ns Units
NOTES: 1 DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input relative to the rising edge of FB_CLK. MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 39
Revision History
Figure 31 shows real-time trace timing for the values in Table 25.
PSTCLK DE0 DE1 PST[3:0] DDATA[3:0] DE2
Figure 31. Real-Time Trace AC Timing
Figure 32 shows BDM serial port AC timing and BKPT pin timing for the values in Table 25.
FB_CLK
DE6
BKPT
DE7
DE5
DSCLK DE3 DSI Current DE4 Next
DSO
Past
Current
Figure 32. BDM Serial Port AC Timing
6
Revision History
Table 26. MCF5373DS Document Revision History
Rev. No. 0 0.1 0.2 * Initial release. * Swapped pin locations PLL_VSS (J11->H11) and DRAMSEL (H11->J11) in Table 3. Figure 1 is correct. * Added not to Section 4, "Mechanicals and Pinouts." * Added "top view" and "bottom view" where appropriate in mechanical drawings and pinout figures. * Figure 10: Corrected "FB_CLK (75MHz)" label to "FB_CLK (80MHz)" * Changed 160QFP pinouts in Figure 3 and Table 3: Removed IRQ3 pin, shifted pins 89-99 up one pin to 90-100. Pin 89 is now VSS. * Table 3: Rearranged GPIO signal names for FEC pins. * Removed ULPI specifications as the device does not support ULPI. Substantive Changes Date of Release 11/2005 12/2005 3/2006
0.3
4/2006
MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 40 Preliminary Freescale Semiconductor
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MCF5373 ColdFire(R) Microprocessor Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary 41
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.(c) Freescale Semiconductor, Inc. 2006. All rights reserved. MCF5373DS Rev. 0.3 04/2006

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